Firmware Information - Quick Links

• DHE Communication link bandwidths
• LCB Clock Sources and Frequencies
• Clock Sources for Master sync clock
• RS232 Communication Channel Command Codes
• Firmware Module Addressing and Identity Codes
• Standard Data Destination Codes for Communication
• Standard Register Addresses for Firmware Modules
• Power Supply Status word definition
• AFE Mezzanine Override register bit definitions
• DheTempSensorSlct Register Value Significance
• Sequencer State Register Bit Assignments for Firmware Modules
• Addresses for I2C Bus Devices / FPGA Boot Code Version Selection
• Bit significance for the LED_1_Slct and LED_2_Slct indicator attributes
• DbgSigSlct attribute values
• Wishbone system status signal assignments for Firmware Modules
  • Local Control Board Module Status Output Assignments
  • Power Supply Services Module Status Output Assignments
  • Configuration Services Module Status Output Assignments
  • Pixel Services Module Status Output Assignments
  • Analog Front End Control Module Status Output Assignments
  • Clock Services Module Status Output Assignments

DHE Communication link bandwidths

There are four communication channels available on the Torrent DHE. The table below shows the available bandwidth for these links and their intended use.

LCB Clock Sources and Frequencies

There are several clock sources available from the LCB clock synthesizer hardware (U28). These clocks provide synchronization to specific areas of the Torrent hardware and firmware. The table below lists the clock name, the nominal frequency and their intended application.

These clocks are derived from U28 (LMK03000) using the following register constants

For DHE Slave operation, where the BCLK frequency is 39.84375 MHz, the value of the Divide by 'R' value changes to 3. All other constants remain the same.

 

Clock Sources for Master sync clock

There are two clock sources available to provide the master OUTSYNC_CLK. The FPGA internally generated source and a source generated directly from the clock synthesizer hardware (U28). These clocks provide synchronization to the slave DHE systems. The table below lists the combinations available by writing to the SyncClkSelect attribute.

 

RS232 Communication Channel Command Codes

The LCB supports an engineering RS232 communication port for engineering use. The available commands (shown below) are prefixed with the 'plus' (+) character (0x2B) and completed with a 'Line Feed' character (0x0A). The standard format of 9600 Baud, 8 bits, no parity is supported. Upper or lower case characters are recognized. All address and data values must be expressed in hex. Fields must be separated by a space or tab character. Backspace clears the current command (although currently the display looks messy).

 

Firmware Module Addressing and Identity Codes

As per ICD 6.1 we use a board select code in each command sent to the LCB to address the individual modules that make up the firmware suit loaded to the Virtex part. This note pretends to fix the identity of the modules selected by each bit of the board select bit field used in the command structure. There are 10 bits available in this field. Torrent currently supports the use of the lowest order five bits although eight bits can be specified (with minor modification) in the Torrent architecture. The table below identifies the correspondence:

 

Standard Data Destination Codes for Communication

The LCB_Control module supplies four duplex channels of communications with the DHE. These four comms channels are: Serial FPTP (Systran Emulation), GIGe (Gigabit ethernet), UART (via serial at 9600 Baud, no handshake), and the SYNC port that links to other slave/master DHE's. The comms destination bits set the required destination for these devices. Setting more than one bit results (mostly !) in parallel transmission to all devices.

 

Standard Register Addresses for Firmware Modules

Each firmware module must supply several registers to support the automatic recognition and configuration processes of the PAN computer. These module addresses are shown below with their functional description:

 

Power Supply Status word definition

The power supply monitors the state of the hardware protection circuits on the LCB-MEZ board. These status bits, when true, indicate a hardware protection fault condition that has interrupted the power supply to one or both of the AFE boards. This status regester is (usually) read as an attribute from the DHE at address 0x016F. The attribute name is PwrSupplyStatus.The status bits and their function definitions are shown below :

 

AFE Mezzanine Override register bit definitions

The mezzanine override register allows you to independently control the AFE power enable bits for the mezzanine board. This is _ONLY_ used for testing purposes since indiscriminate enabling power supplies can cause you to exceed the power supply load capabilities. This register is read and write at address 0x202 in the PSM module

 

DheTempSensorSlct Register Value Significance

This register select which temperature sensor in the DHE is to be used for feedback in the DHE temperature servo loop. The selection of the sensor is based upon a 1 Of 8 (3-bit) code set into the DheTempSensorSlct attribute. The codes are :

 

Sequencer State Register Bit Assignments for Firmware Modules

Each firmware module that requires to know the sequencer state information provides a 32-bit register at address 0xFFF0. The sequencer uses this register to periodically write the sequencer state information to all modules that use this address. The lower 16-bits of the register are static values and may be used to indicate the current mode of the sequencer function (e.g. ROI Readout Mode, Digital Averaging Enabled, etc.). The top 16-bits (31:16) are strobe signals that indicate an event during the sequencer operation (Frame Start, Line Start, etc.) and these bits persist for, and are synchronous to one SysClk cycle before being cancelled. The table below indicates the significance of the Sequencer State Register.

 

Addresses for I2C Bus Devices / FPGA Boot Code Version Selection

There are five I2C buses associated with the Torrent DHE; one I2C bus for every physical board (LCB, PSM, TSM, AFE1, AFE2). There are four devices attached to each bus. This table lists their addresses and describes their use. During the DHE initialization (just after boot), the SDA signal line of each I2C bus is used to detect the presence of the physical board. The SCL signal for AFE1 (AFE_SCL_SRC0) is also used to direct the revision of the code that is booted at power up. This signal is pulled 'high' through a 50K Ohm pullup to 3.3v on the LCB. IR AFE boards should pull this signal low via a 3.3K Ohm resistor to the VPIFC GND return. This will select revision zero of the XF32P eeprom (LCB U43) boot code to load to the FPGA for IR operation. CCD AFE boards should leave this signal floating to select revision 1 of the boot code for VIS operation.

For PAN control of these resources there are several registers that are used to read and write to the I2C devices. These are listed in the following table:

Channel Address values for the physical hardware boards are: LCB = 1, PSM = 2, TSM = 4, AFE1 = 8, AFE2 = 16.

For the ReadI2CBusTemps, ReadI2CBusSerialNumbers, and eepWrtCmdReg commands, multiple channel addresses are allowed (i.e. you can read multiple temperature sensors or write the same data to multiple EEproms using just one command transaction).

For the eepRdCmdReg command, only one unique channel address is allowed.

 

Bit significance for the LED_1_Slct and LED_2_Slct indicator attributes

There are two 8-bit registers assigned to provide visual indication of the internal signals of the FPGA. These registers are read / write. By setting a bit true the indicator (LED1 or LED2) will flash briefly (25ms) every time the selected signal becomes active true. LED1 is currently mounted on the Sync In port connector and LED2 is mounted on the Sync Out Port connector. The tables below indicate the significance of each attribute bit.

 

DbgSigSlct attribute values

This attribute controls the selection of a group of eight signals that are presented on the CFGDATA(7:0) signals (connector J4) on the LCB. By setting the attribute to different values, the hardware debug signals are available for diagnostic use. The attribute accepts values from zero to ten. The list below shows the significance.

These tables list the individual signals for each group.

 

Wishbone system status signal assignments for Firmware Modules

Each firmware module can supply eight bits of 'out of band' status information which is used to transport slow signals (such as static configuration values) to other modules. The routing is controlled by the System Intercon module which employs static assignment to route input status bits to the global 32-bit output status sent to the other modules slave interface. The table below shows the routing information for the system at FPGA version level 2.22.

These next tables show the module status output assignments:

 

Local Control Board Module Status Output Assignments

Power Supply Services Module Status Output Assignments

Configuration Services Module Status Output Assignments

Pixel Services Module Status Output Assignments

 

Analog Front End Control Module Status Output Assignments

Clock Services Module Status Output Assignments