scidoc1152 — Document

Channel Acquisition Board - Firmware version history

November 18, 2010


CCDACQ-12 channel board firmware

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31 July 2006

First pass at a complete redesign. supports basic register set.
Writes to CCD_BIASTELEMETRY, CCD_HVBIASES, and CCD_VOFFSETS are
buffered in a 64-deep FIFO. See *.xls spreadsheet for register defs
and memory map. Does not support "pipelined burst" or any DMA-type
transfers over the SEQ bus. After the ADCs are done converting they
place the data into the CCD_ADCDATA registers. Latency has been
decreased since the slow serial connection to the CPLDs has been
eliminated.

ADC acquire: 2.4us/channel (non-warp mode)
TEL acquire: 22us/channel
Bias or Offset update: 3.5us/channel
Temperature read: 7us

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3 August 2006

reset should now make all LEDs stay on.
added pullup resistors to pipeline_req(7..0) pins which are high-Z.

backplane reads are unreliable... need to look at pix_data timing.

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4 August 2006

Constrain pix_data so that it is stable 12.5ns after the rising edge of
backplane clock. Redesign the large mux in backplane_interface.vhd so that it
is registered prior to driving out on pix_data. Force pix_data registers
and tri-state control register(s) into IOBs for faster turn on. Increase drive
strength to 16mA and add pullup resistors.

Trouble meeting the 4x clock period constraint. Pull the ad_sclk, ad_sync, and
ad_sdata registers out of the IOBs now it meets timing.

pix_data outputs are LVTTL, 16mA, slow slew rate.

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7 August 2006

Previous version garbles backplane reads. Reading back mostly ones, suggesting
that I'm not getting the tri-state buffers enabled soon enough.

Switch to PCI66_3 IO for all inputs attached to the SEQ bus. Note that
VCCO remains at +3.3V, although Xilinx recommends that this is dropped to +3.0V
for full PCI compliance with over/undershoot specs.

pix_data outputs remain LVTTL, 16mA, *FAST* slew rate. Clock to q times of <7ns
are being calculated for the output bus.

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8 August 2006

Still not working... reading back all one's most of the time. In this version
remove the registers after the big mux and use fast tristate buffers on the
output. Meeting clock-to-q contraints of 30ns on pix_data. Still seems to be
only a marginal improvement on paper though. (last interation was 25ns + 7ns)

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14 August 2006

Read operations are completely async and are decoded from seq_data, seq_mode,
and sel_n lines. 30ns after these inputs are stable the ouput data is stable.
This is the fastest, but nastiest implementation to date.


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21 August 2006

Async read logic worked on previous version. Fixed ADC test modes
count and random.


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23 August 2006

add src/backplane/pix_driver.vhd

This module implements the redirect registers and pipeline and burst
mode transfers back to the MCB.

new registers:

add CCD_REDIRECT (24 registers)
add CCD_XFERCOUNT
mod CCD_CTLREG (add burst enable, pipeline enable, and priority bits)
add CCD_BURST
mod CCD_STATUSREG (added pix_busy status bit)

ADC modules now have a timeout so that 5us after GO they return to idle
about 6.4us after a conversion. This is done so that ADCs which are not
present will not hang the board.

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v2.001
29 August 2006

Previous version had some bugs... unstuffed ADC channels were hanging and not
returning to idle. The busy line is grounded on unused channels.

reading CCD_REDIRECT registers returned 0xF, this has been fixed.

In module pix_driver.vhd register pipe_req inputs in pix_driver to
prevent async glitching.

The pix_driver state machine still appears to be getting confused and occasionally
hanging in an unknown state.

Switching over to version numbers, which hopefully will be reflected in the firmware
version register in the firmware.

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v2.002
29 August 2006

change register addresses to be more like Dave's 12 channel design. See the
excel spreadsheet in the /src directory for details.

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v2.003
30 August 2006

Add three read-only CCD_AUDIT registers: CCD_CTC_COUNT, CCD_REQ_COUNT, and
CCD_XFER_COUNT. These counters are cleared with a reset or START_EXPOSURE
command. Add write-only CCD_EVENT_REG register. START_FRAME operation is
not supported. Micro-sequencer is not supported. XMIT_COUNT=1 (aka blogger
mode) is not currently supported.

Offset and Bias interface is broken.

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v2.004
31 August 2006

Right before tristating the pipe_req bus drive it high to produce a sharp rising
edge. This is needed because the pullup resistors aren't strong enough to pull
up the pipe_req signal quickly. The previous version took several hundred ns!
Here's the new sequence:

pipe_req=0xFF, wait 25ns
pipe_req(N)=0, wait 50ns
pipe_req(7)=0, transmit N words out on pix_data.
pipe_req(7)=1, wait 50ns
pipe_req=0xFF, wait 25ns
tristate pipe_req bus

Fixed bug where Offset and Bias DAC rams were not updating. Err, no, this bug is
still here. Making fits files... they look nasty but something is coming out.
pipe_req bus and pix_data bus working ok.

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v2.005
12 September 2006

Offset and Bias DAC RAM async read. Changed the telemetry interface so that
reads from config and data RAMS are async. Now separate read/write address
busses are used everywhere.

Removed the 32x1 RAM module VHDL file from the DAC directory.

Add support for blogger bit. This mode is enabled when xfer_count=1 and
pipe_en=1. In this mode every *other* CTC generates a pipeline transfer back to
the MCB. There will be two pixel values in the tranfer, one old value and one
new value.

The two 18-bit pixels are now packed onto the pix_data bus like this:
pix_data(47..0) <= "000000" & adc_value(17..0) & "000000" & adc_value(17..0)

When the ADCs are put into one of the test modes they will now generate a
brief BUSY pulse to keep the pix_driver module from hanging.

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v2.006
13 September 2006

Fixed the Linear Feedback Shift Register taps to increase the period. For
this LFSR n=32... thus the run length is approaches to 2^32 or 4,294,967,296
samples!

Modify the ADC interface module test counters to respond to the _edge_ of the
go signal, since there is some evidence that the MCB is sending out 50ns wide
32-bit writes (due to a firmware bug).

When the ADCs are put into test mode the latency between the write to the
CCD_CDSREG and the data appearing on the pix_data bus is 325ns. When the
ADCs are in "normal" data mode it should take approximately 2.5us longer.

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v2.007
14 September 2006

Invert all CDS signals.

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v2.008
20 September 2006

Loosen timing constraints for cds_gain<*> outputs. They're basically DC anyway.
Change pin assignments for pix_data<27> and ad_sync<1> in the UCF. This is for
"green wire" mods made the first prototype board.

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v2.009
16 October 2006

Invert the following CDS signals ONLY for channels 0 and 2:
reset, dcrestore, integrate, noninvert, and invert.

add a new register to control the VSUB_SEL resetting at address 0xFFF8.
set any bits in this register to force the VBIAS output high.


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v200A
20 October 2006

Changes to telem16a.vhd: add more wait states and extra clock cycles after
reading out 12 bits from the AD1270 ADC. Increase delay from falling edge
of chip select to first SCLK. Increase delay from last SCLK to rising edge
of chip select, too. Be very conservative.

Rewrite the MAX1270 model to be more accurate and include worst case delays
and use the correct clock edges.

Move telemetry signals out of IOBs because timing is not that critical and
it will then make it possible to place probes on the signals going to the
telemetry ADCs.


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v200B
23 October 2006

Telemetry readback still not working properly in the last version. Redefine
the PD0 and PD1 control bits to mean test mode instead:

+-----+-----+-------------+
| PD1 | PD0 | Mode |
+-----+-----+-------------+
| 0 | 0 | normal data |
| 0 | 1 | all zeros |
| 1 | 0 | 0xC01 |
| 1 | 1 | all ones |
+-----+-----+-------------+

The actual PD1 and PD0 config bits written to the ADC are 0 and 1 respectively.
This forces the ADC into normal operation, external clock, low power standby
mode disabled.

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v200C
23 October 2006

still debugging the telemetry interface...

telem16a: command bits asserted on falling SCLK edges (no change here) but
data bits and strb are sampled on the *rising* edge of SCLK. Write to RAM
delayed by one SCLK cycle.

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v200D
23 October 2006

Found the bug in the telemetry code (telem16a.vhd). The STRB line from the
unselected ADC was floating high, causing the FSM to immediately leave the
wait4strb state and begin counting bits.

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v200E
30 October 2006

Invert the DCRestore signals on channels 0 and 2.

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v200F
27 November 2006

Begin incorportating the sequencer pattern memory. This will work exactly like
the 8ch board. Uses the following register blocks:

CCD_PAT_MEM 0x1000-0x103F
CCD_SEQTRIG 0x0005 (32-bit register)

Pattern memory is 14-bits wide, but expanded out to 16-bits for reading/writing:

[15..8] = delay value in 25ns steps
[7] = external trigger 2
[6] = external trigger 1
[5] = CDS reset
[4] = CDS dc restore
[3] = CDS integrate
[2] = CDS non-invert
[1] = CDS invert
[0] = CTC (fire ADCs)

* user must set the pipeline mode bit if the ADC values are to be transmitted
automatically back to the MCB.

rework the CDSREG and ADCCFG registers extensively. Added new modules:

/seq/seq_top.vhd
/seq/sequencer.vhd
/seq/cds.vhd
/seq/ram64xwd.vhd

Remove ADCSTAT registers since they were unnecessary.

NOTE: the default contents of the Sequencer Pattern Memory are junk. Once we get
closer to the real timing we'll have a better idea of what to put here.

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v2010
28 November 2006

Set the initial contents of the pattern memory to a more logical state.
This is designed for a 4us pixel time. NOTE: all CDS switches are straight
through with no inversion. Move the CDS registers out of the IOBs so we
can attach probes to the pins.

CDS probes added to front panel connector:

GND * * GND
cds_reset * *
cds_dcrestore * *
cds_int * *
cds_noninv * *
cds_inv * *

* *
* *
ext1 * * ext2
GND * * GND

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v2011
7 December 2006 -- "the day that will live in INFAMY!"

Invert CDS signals for channels 1,3-11. This is done in cds.vhd

Change the default sequencer load to Mark's latest 4us timing.

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v2012
13 December 2006

Invert CDS signals for channels ALL CDS channels. Mark's daughterboards are
now using the same analog switch parts.

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v2013
18 December 2006

flip INVERT and NONINVERT pin assignments for channels 0 and 2 in the UCF file.
No changes to logic other than version number update.

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v2014
19 December 2006

We found a bug in the schematic -- flip the INV and NON-INV signals on channels
5 and 7. No changes to logic other than version number update.

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v2015
12 March 2007

Add support for DS2433 4k-bit EEPROM one wire device. This replaces the DS2401
serial number device. (The DS2433 also contains a unique serial number.) Since
the handshaking with this device is fairly complicated a state machine won't cut
it so a small 8-bit micro (PicoBlaze) is used. This micro is programmed in
assembly language.

The DS2433 device is _very_ slow, even in "overdrive" mode. After reset the
EEPROM contents are copied into a 256x16 buffer and then the micro
becomes idle. The micro also reads the 48-bit serial number and checks the
CRC byte at this time. This takes about 100ms.

If the micro is BUSY: the buffer may be read but contents may be invalid; writes
to the buffer will be ignored.

If the micro is IDLE: the buffer is R/W.

When the user asserts SAVE this interrupts the micro and it proceeds to copy
the buffer contents back into the EEPROM memory. This process takes
about 200ms. Afterwards the micro returns to idle.

del misc/serno_interface.vhd
mod backplane/backplane_interface.vhd
mod fpga_top.vhd
add directory owd/
add owd/eeprom.vhd
add owd/kcpsm3.vhd (picoblaze processor)
add owd/prog2433.vhd (note: generated from prog2433.psm)
add owd/ram256x16.vhd

Add new registers NVDAT (256x16) and NVCTL.

other stuff:

mod seq/cds.vhd: remove inversion on INV, NONINV outputs, all channels.
mod seq/seq_top.vhd: insert inverer for CDS_GAIN, all channels.

the old aldec design, new12, appears to be corrupted -- aldec complains of
strange divide by zero errors. copy the source files to a new design called
ccdacq12. modify testbench2 to exercise the eeprom and this checks out OK.

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v2016
22 March 2007

Add internal pullup to the one_wire line. (There is no pullup on the board.)
The DS2433 needs this line pulled high to power the device. The internal
Spartan III pullup is actually pretty good, 4.1k ohms MAX. This meets the
DS2433 device specs.

In the previous version the firmware reads back the serial number and
the NV_DAT buffer is R/W ok. When the NV_CTL register is written we can
see activity on the one_wire bus. However after reset the NV_DAT buffer
is all 0xFFFF. Either the writes are failing or the reads are failing.
change the assembly language program (prog2433.psm) to check the status
of the AA bit after issuing each "COPY SCRATCH" command. If the AA bit
is not set that means that that command failed, and therefore set the
error bit.

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v2017
23 March 2007

Change the assembly language program to use only normal speed routines
and avoid the overdrive mode. Now it works!


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v2018
29 March 2007

Add permanent test points which feature the TRUE logic level for
CDS switches and the ADC start convert signal. The upper nibble of the
board control register specifes the physical channel number to observe.

K19: GAIN
M21: DC Restore
P21: Integrate
T21: Invert
V21: NonInvert
Y21: Reset
AA21: ADC CTC

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v2019
5 April 2007

Write to the CCD_CTLREG register to select which ADC channel probes are brought
out to the front panel like this:

GND o o GND
CDS Gain (K19) o o (K20)
DC Restore (M21) o o (N21)
Integrate (P21) o o (R21)
Invert (T21) o o (U21)
Non-Invert (V21) o o (W21)
CDS Reset (Y21) o o (AA22)
ADC CTC (AA21) o o (AA20)
ADC SCLK (AA19) o o (AA18)
ADC BUSY (AA17) o o (AA16)
ADC SDAT (AA13) o o (AA14)
(AB10) o o (AA10)
(Y10) o o (W10)
(V10) o o (U10)
(T10) o o (R10)
(P10) o o (N10)
(M10) o o (L10)
EXT1 (K10) o o (K11) EXT2
GND o o GND

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v201A
1 November 2007

Clean up UCF file and rebuild under Xilinx ISE 9.2i SP3.
Cosmetic, no changes to functionality other than the version number
has been incremented.

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v201B
1 April 2008

Modify the ADC test mode so that the upper 4 bits are set to the physical
channel number when placed in the "counter" test mode (10).

E.G. physical channel 5 would cycle through:
0101 00000000000000
0101 11111111111111

Add front panel test points for the monsoon backplane bus pins:

GND [ 1] [ 2] GND
CDS Gain (K19) [ 3] [ 4] (K20) sel_n
DC Restore (M21) [ 5] [ 6] (N21) seq_mode0
Integrate (P21) [ 7] [ 8] (R21) seq_mode1
Invert (T21) [ 9] [10] (U21) seq_addr0
Non-Invert (V21) [11] [12] (W21) seq_addr1
CDS Reset (Y21) [13] [14] (AA22) seq_addr2
ADC CTC (AA21) [15] [16] (AA20) seq_data0
ADC SCLK (AA19) [17] [18] (AA18) seq_data1
ADC BUSY (AA17) [19] [20] (AA16) seq_data2
ADC SYNC (AA15) [21] [22] (AA14) seq_data3
ADC SDAT (AA13) [23] [24] (AA12) seq_data4
(AB10) [25] [26] (AA10) seq_data5
(Y10) [27] [28] (W10) seq_data6
(V10) [29] [30] (U10) seq_data7
(T10) [31] [32] (R10)
(P10) [33] [34] (N10)
(M10) [35] [36] (L10)
EXT1 (K10) [37] [38] (K11) EXT2
GND [39] [40] GND

*** note that the new sequencer diagnostic test points are
registered copies of the bus signals!

built using ISE 9.2i SP4

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v201C
2 April 2008

Fix front panel testpoint pinout errors:

Name FPGA PIN PIN FPGA Name
---------- ------ --- --- ------ ---------
GND [ 1] [ 2] GND
CDS Gain (K19) [ 3] [ 4] (K20) sel_n
DC Restore (M21) [ 5] [ 6] (N21) seq_mode0
Integrate (P21) [ 7] [ 8] (R21) seq_mode1
Invert (T21) [ 9] [10] (U21) seq_addr0
Non-Invert (V21) [11] [12] (W21) seq_addr1
CDS Reset (Y21) [13] [14] (AA22) seq_addr2
ADC CTC (AA21) [15] [16] (AA20) seq_data0
ADC SCLK (AA19) [17] [18] (AA18) seq_data1
ADC BUSY (AA17) [19] [20] (AA16) seq_data2
ADC SYNC (AA15) [21] [22] (AA14) seq_data3
ADC SDAT (AA13) [23] [24] (AA12) seq_data4
(AB10) [25] [26] (AA10) seq_data5
(Y10) [27] [28] (W10) seq_data6
(V10) [29] [30] (U10) seq_data7
(T10) [31] [32] (R10)
(P10) [33] [34] (N10)
(M10) [35] [36] (L10)
EXT1 (K10) [37] [38] (K11) EXT2
GND [39] [40] GND


Verified that the ADC CTC testpoint on the front panel (pin 15, FPGA AA21)
is cds_test(6) which is really physically connected to the ADC CTC line!



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v201D
4 April 2008

Fixed bugs in the audit registers:

CCD_CTC_COUNT: the number of CTC strobes generated by writes to the CCD_CDSREG
register or by the on-board microsequencer.

CCD_REQ_COUNT: the number of times a pipeline request has been made to the
MCB in pipeline mode.

CCD_XFER_COUNT: the total number of pixels transferred to the MCB. Note that
this register simply accumulates the value of CCD_XFERCOUNT
each time pixels are transferred in pipeline mode.

NOTE: minimum time between CTC strobes is approximately 2.4us. This was
determined in pipeline mode with the ADCs in normal (not WARP) mode.

Add new testpoint "PIXEL_XMIT" which is set whenever pixels
are transmitted are on the pixel bus. Test points are:

Name FPGA PIN PIN FPGA Name
---------- ------ --- --- ------ ---------
GND [ 1] [ 2] GND
CDS Gain (K19) [ 3] [ 4] (K20) sel_n
DC Restore (M21) [ 5] [ 6] (N21) seq_mode0
Integrate (P21) [ 7] [ 8] (R21) seq_mode1
Invert (T21) [ 9] [10] (U21) seq_addr0
Non-Invert (V21) [11] [12] (W21) seq_addr1
CDS Reset (Y21) [13] [14] (AA22) seq_addr2
ADC CTC (AA21) [15] [16] (AA20) seq_data0
ADC SCLK (AA19) [17] [18] (AA18) seq_data1
ADC BUSY (AA17) [19] [20] (AA16) seq_data2
ADC SYNC (AA15) [21] [22] (AA14) seq_data3
ADC SDAT (AA13) [23] [24] (AA12) seq_data4
PIXEL_XMIT (AB10) [25] [26] (AA10) seq_data5
(Y10) [27] [28] (W10) seq_data6
(V10) [29] [30] (U10) seq_data7
(T10) [31] [32] (R10)
(P10) [33] [34] (N10)
(M10) [35] [36] (L10)
EXT1 (K10) [37] [38] (K11) EXT2
GND [39] [40] GND



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v201E
7 April 2008

Shorten the timeout value in the adc_interface module. Wait 2.5us for the start
of the ADC busy and then wait for 2.5us for ADC to return to idle. If the ADC
busy line is stuck the ADC interface module will incurr one of the timeout
periods and fall though.

A problem was recently encountered when the 12-ch board was driven faster than
6us with some channels empty. Every second CTC cycle was ignored because some of
the ADC modules were busy waiting on ADCs that were not stuffed. This resulted
in the PAN computer receiving only 1/2 of the pixel data.

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v201F
11 April 2008

Add a buffer that stores up to 1024 commands written to the board. This is
conventional memory that must be cleared and addressed explicitly. (The
buffer is automatically cleared after a reset.) Once the buffer is filled
no more commands are stored until the buffer is cleared. Everything is
accessed through four registers:

CCD_CAPCTRL : control/status register
CCD_CAPADDR : address register RO
CCD_CAPDAT0 : low data word RO
CCD_CAPDAT1 : high data word RO

Control/Status Register bits:

15: Clear Buffer W/O
14: W16 flag R/O
13: W32 flag R/O
12-10: zero
09-00: address pointer R/W

How to use it:
1. write 0x8000 to CCD_CAPCTRL to clear the buffer
2. write a bunch of regular commands to the board
3. Dump the command buffer:
for i=0 to 1023
{
write i to CCD_CAPCTRL
read CCD_CAPCTRL
read CCD_CAPADDR
read CCD_CAPDAT1
read CCD_CAPDAT0
}

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v2020
2 May 2008

Change pin assignment for the temperature sensor for the rev 2 boards.

It was this way:

temp_dout AB19
temp_sclk AC18
temp_cs_n AB16

where the chip select pin was lifted and tied to the DIN pin.

Now the temp sensor is connected like this:

temp_dout AB19
temp_sclk AC18
temp_cs_n AD20
temp_din AB16

Add a new pin called temp_din and make it functionally the same as
temp_cs, that should work for both the new and old boards.

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v2021
12 June 2008

Change pin assignment PixD(27) from pin C27 (a test point) to pin A16. This
goes back to a green wire mod on the original 12 ch proto boards.
Other pinout changes:

ad_sync<1> moved from G25 to B16.

cds_invert<0> loc = g14
cds_noninvert<0> loc = h15

cds_invert<2> loc = d29
cds_noninvert<2> loc = d28

cds_invert<5> loc = y27
cds_noninvert<5> loc = ab27

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v2022
28 August 2008

The reboot logic has been disabled because it was discovered that having the
FPGA pull it's own PROG_B line low (to erase and reload) was not stable.
There was no way to guarantee a minimum period on the PROG_B line and sometimes
the FPGA would not reload properly. At minimum an external cap is needed to
make this work; active circuitry such as a one shot would be better. This
feature is disabled for now until we know that we really need it.

Verified that the full 48-bit serial number is sent out on the pixel bus.
(The questions is: can the MCB/PAN read back a full 48-bit number???)

Added support for data select bits in the board control register. This allows
for various combinations of 16/18 bit pixel values to be sent in pipeline
and burst transfer modes. Verified that it works in blogger mode. Power on
default for these bits are "00" which is to send the lower 16 bits of each
18-bit pixel value.

CCD_DATASLCT pixel_data_bus(47..0)
------------ ----------------------------------------------------------
0 (default) X"00" + high_pixel(15..0) + X"00" + low_pixel(15..0)
1 X"00" + high_pixel(16..1) + X"00" + low_pixel(16..1)
2 X"00" + high_pixel(17..2) + X"00" + low_pixel(17..2)
3 "000000" + high_pixel(17..0) + "000000" + low_pixel(17..0)

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v2023
09 October 2008

Fixed a bug in the CDS switch outputs. The INVERT and NONINVERT signals
are now ACTIVE LOW to match the 8ch board.

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v2024
6 January 2009

Modify the backplane read logic so that reads are double-registered and forced
into IOBs in the chip. Read latency is increased compared to prior fully-async
real logic incarnations. Will test now...

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v2025
7 January 2009

Previous version is not fast enough. Reading back all 1's. Try "pre-driving"
the pix_data bus with a signal from the first level of flops.

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v2026
7 January 2009

register backplane inputs and leave the pix_data muxing and tri-state drivers
driven from input flops.

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v2027
15 January 2009

Double register the read logic, tighter constraints on the ACK output. Change
ack_n output from open-drain w/ pullup to a totem pole output.


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v2028
29 January 2009

Return to async read logic, tighten up timing constraints and read mux
simplification using don't care masking.

redirect registers are now in RAM and are NOT affected by a hard reset.

Constrain read latency to 25ns.

simplify reset module

ADC data reg forced to zero upon reset.

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v2029
4 February 2009

add new CCDADC test modes:

00 = normal data (default)
01 = all zeros
10 = board_priority + physical_channel + counter
11 = pseudorandom[17..0]

18 bit pixel max count is 262143

In test mode "10" the counts are reported in decimal form xxyyzz
where xx = board priority 00-06
yy = physical channel number 00-11
zz = counter 00-99

e.g. (priority*10000) + (physical_channel*100) + count

tighter timing constraints on the pixel data bus driver tri-state lines


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v202A
5 February 2009

Fixed a bug in the backplane interface where the redirect registers were
updating with every backplane write, this would result with the redirect
registers filling up with garbage and trashing the pipeline and burst
modes.

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v202B
9 February 2009

The pixel driver logic is buggy for multiple boards and is not asserting
pipe_req signals properly. This has been fixed in this release. Remove
obsolete "blogger mode" functionality in the pixel driver.

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v202C
12 February 2009

Monitor the "shutdown" signal from the transition card on FPGA pin K14.
This pin is sampled and may be read in the board status register, bit 10.

fix bug in the board status register where the sequencer busy flag is now
in the correct place (bit 8)

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v202D
8 April 2009

Fixed bugs in sequencer.vhd

Microsequencer latency is 75ns measured as write to the CCD_SEQTRIG register
to first vector out. A delay value of 0 is 25ns, 1 = 50ns, ... 255 = 6.4us

If the last vector in the sequence triggers the ADC conversion, this bit
will be automatically cleared as the sequencer returns to idle. This is to
prevent the ADCs from converting continously after the microsequncer stops.

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v202E
27 April 2009

Scott discovered a bug that shows up when writing to offset DACs that don't
exist... e.g. writing to addresses 0x21C-0x21F the DAC module hangs waiting
for DACs that don't exist to go busy!

Problem is that the FIFO in the DAC module accepts writes to offset
channels above 0x21B, but the logic reading from the FIFO doesn't know
what to do with these DAC channels, so it does nothing and the FIFO stays
busy forever. Fixed in this release.


--------------------------------------------------------------------------------
v202F
17 August 2009

Fix EXT1 and EXT2 flip in seq/cds.vhd

Fixed bug in sequencer where it would write 0x00 to the CDS register
at the beginning and end of sequence. Now first/last states are properly
written to the CDS register with no glitching.

NOTE: did not find anything wrong with the physical/logical channel
mapping and the CDS register.

This version number may be reported as 82.39.

--------------------------------------------------------------------------------
v4.00
6 October 2009

Change the versioning numbering to be consistant with other Monsoon boards
which use a floating point scheme. e.g. 0x202F = 8239 which is reported
as 82.39. Starting in this verson it will be 4.00 which is 0x190.
Update only the ccdacq_package.vhd, no functional changes to the design.

--------------------------------------------------------------------------------
v4.02
24 February 2010

Change to async reset on the control bits in the aux_cfg_reg and vbias_reg
registers. This should prevent any unusual spikes in the bias voltages and
in vsub rails during powerup. (There is no evidence that this is harming
the CCDs but we want to safe just in case.)

The default CCLK ConfigRate was set to 6MHz and config time was LONG at
1.5 seconds. Changed it to 25MHz to reduce configuration time on power up.


--------------------------------------------------------------------------------
v4.03
3 March 2010

Change the CCD_AUXCFGREG so that bias_en(0) is controlled by CCD_AUXCFGREG(2).
CCD_AUXCFGREG(1) still controls bias_en(2) and bias_en(1). Config rate is
25MHz with bitstream compression turned OFF.


--------------------------------------------------------------------------------
v4.04
22 September 2010

Possible CCD damage caused by VSUB going negative. Add in a check that limits
DAC writes to channel 0 (VSUB limit) in the range of 0x333 - 0xFFF. If the user
writes to DAC channel 0 AND the data value is < 0x333 the write will
occur but the data will be 0x333.

Also force the BIAS CLSEL(0) line to HIGH. This will set the BIAS DACs (ch0-ch7)
to midscale IF they are RESET. It does not matter what the user writes to
AUXCFGREG bit 6 -- it will always be high.

--------------------------------------------------------------------------------
v4.05
22 September 2010

Add "engineering mode" bit to AUXCFGREG bit 15. When this bit is set it unlocks
the BIAS and OFFSET mode and reset controls in AUXCFGREG. Also, when this bit
is set it allows unrestricted writes to DAC channel 0 (VSUB).

eng_mode = 1
--------------------------------------
bias and offset CLSEL = user controlled
bias and offset RESET = user controlled
bias DAC channel 0 (vsub) = unrestricted

eng_mode = 0
--------------------------------------
bias and offset CLSEL = 1 (midscale)
bias and offset RESET = 0 (disabled)
bias DAC channel 0 (vsub) = range restricted to 0x333-0xfff

--------------------------------------------------------------------------------
v4.06
23 September 2010

Forget engineering mode. Remove the DAC reset functionality and tie the CLSEL
lines high (mid-scale) and tie the DAC reset lines low. Remove these controls
from the AUXCFGREG.

Impose restrictions on all DAC channels:

VSUB limit/ramp range from 0V (0x333) to 40V (0xFFF)
VDD range from -25V (0x001) to 0V (0xccb)
VOG range from 0V (0x551) to 5V (0xFF5)
VR range from -15V (0x000) to 0V (0x222)

Bias channel 0 = VBIAS limit
Bias channel 1 = VBIAS ramp rate
ch16-23 = VRU
ch24-31 = VRL
CH32-39 = Vog
ch40-47 = VDD

--------------------------------------------------------------------------------
v4.07
5 October 2010

Remove the DAC channel limits. The DAC reset and mode (zero or mid-scale)
control lines are still disabled.

--------------------------------------------------------------------------------
v4.08
18 November 2010

"blackout" features -- because we don't want all of those photons lurking
about in the observatory!

LEDs default to OFF and must be enabled by writing to the LED register.
Also LEDs are OFF during RESET.






About the Document

Id: scidoc1152
Release date: November 18, 2010, 5:13 pm

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