Design Overview for cb_fpga

PropertyValue
Project Name:/home/user/testclk/CBv4.01
Target Device:xc2s200
Report Generated:Thursday 03/31/11 at 07:03
Printable Summary (View as HTML)cb_fpga_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:7044,70414% 
Number of 4 input LUTs:1,2694,70426% 
Logic Distribution:    
Number of occupied Slices:8972,35238% 
Number of Slices containing only related logic:897897100% 
Number of Slices containing unrelated logic:08970% 
Total Number 4 input LUTs:1,3554,70428% 
Number used as logic:1,269   
Number used as a route-thru:85   
Number used as Shift registers:1   
Number of bonded IOBs:20228471% 
Number of Tbufs:22,4641% 
Number of Block RAMs:41428% 
Number of GCLKs:1425% 
Number of GCLKIOBs:1425% 

Performance Summary

PropertyValue
Final Timing Score:0
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
All Constraints Met   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentThursday 03/31/11 at 07:02
Translation ReportCurrentThursday 03/31/11 at 07:02
Map ReportCurrentThursday 03/31/11 at 07:02
Pad ReportCurrentThursday 03/31/11 at 07:03
Place and Route ReportCurrentThursday 03/31/11 at 07:03
Post Place and Route Static Timing ReportCurrentThursday 03/31/11 at 07:03
Bitgen ReportCurrentThursday 03/31/11 at 07:03