| Property | Value |
| Project Name: | /home/user/testclk/CBv4.01 |
| Target Device: | xc2s200 |
| Report Generated: | Thursday 03/31/11 at 07:03 |
| Printable Summary (View as HTML) | cb_fpga_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops: | 704 | 4,704 | 14% | |
| Number of 4 input LUTs: | 1,269 | 4,704 | 26% | |
| Logic Distribution: | ||||
| Number of occupied Slices: | 897 | 2,352 | 38% | |
| Number of Slices containing only related logic: | 897 | 897 | 100% | |
| Number of Slices containing unrelated logic: | 0 | 897 | 0% | |
| Total Number 4 input LUTs: | 1,355 | 4,704 | 28% | |
| Number used as logic: | 1,269 | |||
| Number used as a route-thru: | 85 | |||
| Number used as Shift registers: | 1 | |||
| Number of bonded IOBs: | 202 | 284 | 71% | |
| Number of Tbufs: | 2 | 2,464 | 1% | |
| Number of Block RAMs: | 4 | 14 | 28% | |
| Number of GCLKs: | 1 | 4 | 25% | |
| Number of GCLKIOBs: | 1 | 4 | 25% |
| Property | Value |
| Final Timing Score: | 0 |
| Number of Unrouted Signals: | All signals are completely routed. |
| Number of Failing Constraints: | 0 |
| Constraint(s) | Requested | Actual | Logic Levels |
| All Constraints Met |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Thursday 03/31/11 at 07:02 |
| Translation Report | Current | Thursday 03/31/11 at 07:02 |
| Map Report | Current | Thursday 03/31/11 at 07:02 |
| Pad Report | Current | Thursday 03/31/11 at 07:03 |
| Place and Route Report | Current | Thursday 03/31/11 at 07:03 |
| Post Place and Route Static Timing Report | Current | Thursday 03/31/11 at 07:03 |
| Bitgen Report | Current | Thursday 03/31/11 at 07:03 |